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  2. /dts-v1/;
  4. / {
  5. #address-cells = < 0x02 >;
  6. #size-cells = < 0x02 >;
  7. compatible = "asus,rk3288-tinker\0rockchip,rk3288";
  8. interrupt-parent = < 0x01 >;
  9. model = "Rockchip RK3288 Tinker Board";
  11. aliases {
  12. ethernet0 = "/ethernet@ff290000";
  13. i2c0 = "/i2c@ff650000";
  14. i2c1 = "/i2c@ff140000";
  15. i2c2 = "/i2c@ff660000";
  16. i2c3 = "/i2c@ff150000";
  17. i2c4 = "/i2c@ff160000";
  18. i2c5 = "/i2c@ff170000";
  19. mshc0 = "/dwmmc@ff0f0000";
  20. mshc1 = "/dwmmc@ff0c0000";
  21. mshc2 = "/dwmmc@ff0d0000";
  22. mshc3 = "/dwmmc@ff0e0000";
  23. serial0 = "/serial@ff180000";
  24. serial1 = "/serial@ff190000";
  25. serial2 = "/serial@ff690000";
  26. serial3 = "/serial@ff1b0000";
  27. serial4 = "/serial@ff1c0000";
  28. spi0 = "/spi@ff110000";
  29. spi1 = "/spi@ff120000";
  30. spi2 = "/spi@ff130000";
  31. };
  33. arm-pmu {
  34. compatible = "arm,cortex-a12-pmu";
  35. interrupts = < 0x00 0x97 0x04 0x00 0x98 0x04 0x00 0x99 0x04 0x00 0x9a 0x04 >;
  36. interrupt-affinity = < 0x02 0x03 0x04 0x05 >;
  37. };
  39. cpus {
  40. #address-cells = < 0x01 >;
  41. #size-cells = < 0x00 >;
  42. enable-method = "rockchip,rk3066-smp";
  43. rockchip,pmu = < 0x06 >;
  45. cpu@500 {
  46. device_type = "cpu";
  47. compatible = "arm,cortex-a12";
  48. reg = < 0x500 >;
  49. resets = < 0x07 0x00 >;
  50. operating-points = < 0x188940 0x149970 0x171240 0x13d620 0x159b40 0x124f80 0x124f80 0x10c8e0 0xf6180 0x100590 0xc7380 0xf4240 0xa9ec0 0xe7ef0 0x927c0 0xdbba0 0x639c0 0xdbba0 0x4c2c0 0xdbba0 0x34bc0 0xdbba0 0x1ec30 0xdbba0 >;
  51. #cooling-cells = < 0x02 >;
  52. clock-latency = < 0x9c40 >;
  53. clocks = < 0x07 0x06 >;
  54. cpu0-supply = < 0x08 >;
  55. phandle = < 0x02 >;
  56. };
  58. cpu@501 {
  59. device_type = "cpu";
  60. compatible = "arm,cortex-a12";
  61. reg = < 0x501 >;
  62. resets = < 0x07 0x01 >;
  63. phandle = < 0x03 >;
  64. };
  66. cpu@502 {
  67. device_type = "cpu";
  68. compatible = "arm,cortex-a12";
  69. reg = < 0x502 >;
  70. resets = < 0x07 0x02 >;
  71. phandle = < 0x04 >;
  72. };
  74. cpu@503 {
  75. device_type = "cpu";
  76. compatible = "arm,cortex-a12";
  77. reg = < 0x503 >;
  78. resets = < 0x07 0x03 >;
  79. phandle = < 0x05 >;
  80. };
  81. };
  83. amba {
  84. compatible = "simple-bus";
  85. #address-cells = < 0x02 >;
  86. #size-cells = < 0x02 >;
  87. ranges;
  89. dma-controller@ff250000 {
  90. compatible = "arm,pl330\0arm,primecell";
  91. reg = < 0x00 0xff250000 0x00 0x4000 >;
  92. interrupts = < 0x00 0x02 0x04 0x00 0x03 0x04 >;
  93. #dma-cells = < 0x01 >;
  94. arm,pl330-broken-no-flushp;
  95. clocks = < 0x07 0xc2 >;
  96. clock-names = "apb_pclk";
  97. phandle = < 0x1b >;
  98. };
  100. dma-controller@ff600000 {
  101. compatible = "arm,pl330\0arm,primecell";
  102. reg = < 0x00 0xff600000 0x00 0x4000 >;
  103. interrupts = < 0x00 0x00 0x04 0x00 0x01 0x04 >;
  104. #dma-cells = < 0x01 >;
  105. arm,pl330-broken-no-flushp;
  106. clocks = < 0x07 0xc1 >;
  107. clock-names = "apb_pclk";
  108. status = "disabled";
  109. };
  111. dma-controller@ffb20000 {
  112. compatible = "arm,pl330\0arm,primecell";
  113. reg = < 0x00 0xffb20000 0x00 0x4000 >;
  114. interrupts = < 0x00 0x00 0x04 0x00 0x01 0x04 >;
  115. #dma-cells = < 0x01 >;
  116. arm,pl330-broken-no-flushp;
  117. clocks = < 0x07 0xc1 >;
  118. clock-names = "apb_pclk";
  119. phandle = < 0x5b >;
  120. };
  121. };
  123. reserved-memory {
  124. #address-cells = < 0x02 >;
  125. #size-cells = < 0x02 >;
  126. ranges;
  128. dma-unusable@fe000000 {
  129. reg = < 0x00 0xfe000000 0x00 0x1000000 >;
  130. };
  131. };
  133. oscillator {
  134. compatible = "fixed-clock";
  135. clock-frequency = < 0x16e3600 >;
  136. clock-output-names = "xin24m";
  137. #clock-cells = < 0x00 >;
  138. phandle = < 0x09 >;
  139. };
  141. timer {
  142. compatible = "arm,armv7-timer";
  143. arm,cpu-registers-not-fw-configured;
  144. interrupts = < 0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04 >;
  145. clock-frequency = < 0x16e3600 >;
  146. };
  148. timer@ff810000 {
  149. compatible = "rockchip,rk3288-timer";
  150. reg = < 0x00 0xff810000 0x00 0x20 >;
  151. interrupts = < 0x00 0x48 0x04 >;
  152. clocks = < 0x09 0x07 0x161 >;
  153. clock-names = "timer\0pclk";
  154. };
  156. display-subsystem {
  157. compatible = "rockchip,display-subsystem";
  158. ports = < 0x0a 0x0b >;
  159. };
  161. dwmmc@ff0c0000 {
  162. compatible = "rockchip,rk3288-dw-mshc";
  163. max-frequency = < 0x8f0d180 >;
  164. clocks = < 0x07 0x1c8 0x07 0x44 0x07 0x72 0x07 0x76 >;
  165. clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
  166. fifo-depth = < 0x100 >;
  167. interrupts = < 0x00 0x20 0x04 >;
  168. reg = < 0x00 0xff0c0000 0x00 0x4000 >;
  169. resets = < 0x07 0x80 >;
  170. reset-names = "reset";
  171. status = "okay";
  172. bus-width = < 0x04 >;
  173. cap-mmc-highspeed;
  174. cap-sd-highspeed;
  175. card-detect-delay = < 0xc8 >;
  176. disable-wp;
  177. pinctrl-names = "default";
  178. pinctrl-0 = < 0x0c 0x0d 0x0e 0x0f >;
  179. vmmc-supply = < 0x10 >;
  180. vqmmc-supply = < 0x11 >;
  181. };
  183. dwmmc@ff0d0000 {
  184. compatible = "rockchip,rk3288-dw-mshc";
  185. max-frequency = < 0x8f0d180 >;
  186. clocks = < 0x07 0x1c9 0x07 0x45 0x07 0x73 0x07 0x77 >;
  187. clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
  188. fifo-depth = < 0x100 >;
  189. interrupts = < 0x00 0x21 0x04 >;
  190. reg = < 0x00 0xff0d0000 0x00 0x4000 >;
  191. resets = < 0x07 0x81 >;
  192. reset-names = "reset";
  193. status = "okay";
  194. clock-frequency = < 0x2faf080 >;
  195. clock-freq-min-max = < 0x30d40 0x2faf080 >;
  196. bus-width = < 0x04 >;
  197. cap-sd-highspeed;
  198. cap-sdio-irq;
  199. disable-wp;
  200. keep-power-in-suspend;
  201. mmc-pwrseq = < 0x12 >;
  202. non-removable;
  203. num-slots = < 0x01 >;
  204. pinctrl-names = "default";
  205. pinctrl-0 = < 0x13 0x14 0x15 >;
  206. sd-uhs-sdr104;
  207. supports-sdio;
  208. };
  210. dwmmc@ff0e0000 {
  211. compatible = "rockchip,rk3288-dw-mshc";
  212. max-frequency = < 0x8f0d180 >;
  213. clocks = < 0x07 0x1ca 0x07 0x46 0x07 0x74 0x07 0x78 >;
  214. clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
  215. fifo-depth = < 0x100 >;
  216. interrupts = < 0x00 0x22 0x04 >;
  217. reg = < 0x00 0xff0e0000 0x00 0x4000 >;
  218. resets = < 0x07 0x82 >;
  219. reset-names = "reset";
  220. status = "disabled";
  221. };
  223. dwmmc@ff0f0000 {
  224. compatible = "rockchip,rk3288-dw-mshc";
  225. max-frequency = < 0x8f0d180 >;
  226. clocks = < 0x07 0x1cb 0x07 0x47 0x07 0x75 0x07 0x79 >;
  227. clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
  228. fifo-depth = < 0x100 >;
  229. interrupts = < 0x00 0x23 0x04 >;
  230. reg = < 0x00 0xff0f0000 0x00 0x4000 >;
  231. resets = < 0x07 0x83 >;
  232. reset-names = "reset";
  233. status = "okay";
  234. bus-width = < 0x08 >;
  235. cap-mmc-highspeed;
  236. disable-wp;
  237. non-removable;
  238. num-slots = < 0x01 >;
  239. pinctrl-names = "default";
  240. pinctrl-0 = < 0x16 0x17 0x18 0x19 >;
  241. mmc-hs200-1_8v;
  242. mmc-ddr-1_8v;
  243. };
  245. saradc@ff100000 {
  246. compatible = "rockchip,saradc";
  247. reg = < 0x00 0xff100000 0x00 0x100 >;
  248. interrupts = < 0x00 0x24 0x04 >;
  249. #io-channel-cells = < 0x01 >;
  250. clocks = < 0x07 0x49 0x07 0x15b >;
  251. clock-names = "saradc\0apb_pclk";
  252. resets = < 0x07 0x57 >;
  253. reset-names = "saradc-apb";
  254. status = "okay";
  255. vref-supply = < 0x1a >;
  256. };
  258. spi@ff110000 {
  259. compatible = "rockchip,rk3288-spi\0rockchip,rk3066-spi";
  260. clocks = < 0x07 0x41 0x07 0x152 >;
  261. clock-names = "spiclk\0apb_pclk";
  262. dmas = < 0x1b 0x0b 0x1b 0x0c >;
  263. dma-names = "tx\0rx";
  264. interrupts = < 0x00 0x2c 0x04 >;
  265. pinctrl-names = "default";
  266. pinctrl-0 = < 0x1c 0x1d 0x1e 0x1f >;
  267. reg = < 0x00 0xff110000 0x00 0x1000 >;
  268. #address-cells = < 0x01 >;
  269. #size-cells = < 0x00 >;
  270. status = "disabled";
  271. };
  273. spi@ff120000 {
  274. compatible = "rockchip,rk3288-spi\0rockchip,rk3066-spi";
  275. clocks = < 0x07 0x42 0x07 0x153 >;
  276. clock-names = "spiclk\0apb_pclk";
  277. dmas = < 0x1b 0x0d 0x1b 0x0e >;
  278. dma-names = "tx\0rx";
  279. interrupts = < 0x00 0x2d 0x04 >;
  280. pinctrl-names = "default";
  281. pinctrl-0 = < 0x20 0x21 0x22 0x23 >;
  282. reg = < 0x00 0xff120000 0x00 0x1000 >;
  283. #address-cells = < 0x01 >;
  284. #size-cells = < 0x00 >;
  285. status = "disabled";
  286. };
  288. spi@ff130000 {
  289. compatible = "rockchip,rk3288-spi\0rockchip,rk3066-spi";
  290. clocks = < 0x07 0x43 0x07 0x154 >;
  291. clock-names = "spiclk\0apb_pclk";
  292. dmas = < 0x1b 0x0f 0x1b 0x10 >;
  293. dma-names = "tx\0rx";
  294. interrupts = < 0x00 0x2e 0x04 >;
  295. pinctrl-names = "default";
  296. pinctrl-0 = < 0x24 0x25 0x26 0x27 >;
  297. reg = < 0x00 0xff130000 0x00 0x1000 >;
  298. #address-cells = < 0x01 >;
  299. #size-cells = < 0x00 >;
  300. status = "disabled";
  301. };
  303. i2c@ff140000 {
  304. compatible = "rockchip,rk3288-i2c";
  305. reg = < 0x00 0xff140000 0x00 0x1000 >;
  306. interrupts = < 0x00 0x3e 0x04 >;
  307. #address-cells = < 0x01 >;
  308. #size-cells = < 0x00 >;
  309. clock-names = "i2c";
  310. clocks = < 0x07 0x14d >;
  311. pinctrl-names = "default";
  312. pinctrl-0 = < 0x28 >;
  313. status = "disabled";
  314. };
  316. i2c@ff150000 {
  317. compatible = "rockchip,rk3288-i2c";
  318. reg = < 0x00 0xff150000 0x00 0x1000 >;
  319. interrupts = < 0x00 0x3f 0x04 >;
  320. #address-cells = < 0x01 >;
  321. #size-cells = < 0x00 >;
  322. clock-names = "i2c";
  323. clocks = < 0x07 0x14f >;
  324. pinctrl-names = "default";
  325. pinctrl-0 = < 0x29 >;
  326. status = "disabled";
  327. };
  329. i2c@ff160000 {
  330. compatible = "rockchip,rk3288-i2c";
  331. reg = < 0x00 0xff160000 0x00 0x1000 >;
  332. interrupts = < 0x00 0x40 0x04 >;
  333. #address-cells = < 0x01 >;
  334. #size-cells = < 0x00 >;
  335. clock-names = "i2c";
  336. clocks = < 0x07 0x150 >;
  337. pinctrl-names = "default";
  338. pinctrl-0 = < 0x2a >;
  339. status = "disabled";
  340. };
  342. i2c@ff170000 {
  343. compatible = "rockchip,rk3288-i2c";
  344. reg = < 0x00 0xff170000 0x00 0x1000 >;
  345. interrupts = < 0x00 0x41 0x04 >;
  346. #address-cells = < 0x01 >;
  347. #size-cells = < 0x00 >;
  348. clock-names = "i2c";
  349. clocks = < 0x07 0x151 >;
  350. pinctrl-names = "default";
  351. pinctrl-0 = < 0x2b >;
  352. status = "okay";
  353. phandle = < 0x71 >;
  354. };
  356. serial@ff180000 {
  357. compatible = "rockchip,rk3288-uart\0snps,dw-apb-uart";
  358. reg = < 0x00 0xff180000 0x00 0x100 >;
  359. interrupts = < 0x00 0x37 0x04 >;
  360. reg-shift = < 0x02 >;
  361. reg-io-width = < 0x04 >;
  362. clocks = < 0x07 0x4d 0x07 0x155 >;
  363. clock-names = "baudclk\0apb_pclk";
  364. pinctrl-names = "default";
  365. pinctrl-0 = < 0x2c 0x2d >;
  366. status = "okay";
  367. };
  369. serial@ff190000 {
  370. compatible = "rockchip,rk3288-uart\0snps,dw-apb-uart";
  371. reg = < 0x00 0xff190000 0x00 0x100 >;
  372. interrupts = < 0x00 0x38 0x04 >;
  373. reg-shift = < 0x02 >;
  374. reg-io-width = < 0x04 >;
  375. clocks = < 0x07 0x4e 0x07 0x156 >;
  376. clock-names = "baudclk\0apb_pclk";
  377. pinctrl-names = "default";
  378. pinctrl-0 = < 0x2e >;
  379. status = "okay";
  380. };
  382. serial@ff690000 {
  383. compatible = "rockchip,rk3288-uart\0snps,dw-apb-uart";
  384. reg = < 0x00 0xff690000 0x00 0x100 >;
  385. interrupts = < 0x00 0x39 0x04 >;
  386. reg-shift = < 0x02 >;
  387. reg-io-width = < 0x04 >;
  388. clocks = < 0x07 0x4f 0x07 0x157 >;
  389. clock-names = "baudclk\0apb_pclk";
  390. pinctrl-names = "default";
  391. pinctrl-0 = < 0x2f >;
  392. status = "okay";
  393. };
  395. serial@ff1b0000 {
  396. compatible = "rockchip,rk3288-uart\0snps,dw-apb-uart";
  397. reg = < 0x00 0xff1b0000 0x00 0x100 >;
  398. interrupts = < 0x00 0x3a 0x04 >;
  399. reg-shift = < 0x02 >;
  400. reg-io-width = < 0x04 >;
  401. clocks = < 0x07 0x50 0x07 0x158 >;
  402. clock-names = "baudclk\0apb_pclk";
  403. pinctrl-names = "default";
  404. pinctrl-0 = < 0x30 >;
  405. status = "okay";
  406. };
  408. serial@ff1c0000 {
  409. compatible = "rockchip,rk3288-uart\0snps,dw-apb-uart";
  410. reg = < 0x00 0xff1c0000 0x00 0x100 >;
  411. interrupts = < 0x00 0x3b 0x04 >;
  412. reg-shift = < 0x02 >;
  413. reg-io-width = < 0x04 >;
  414. clocks = < 0x07 0x51 0x07 0x159 >;
  415. clock-names = "baudclk\0apb_pclk";
  416. pinctrl-names = "default";
  417. pinctrl-0 = < 0x31 >;
  418. status = "okay";
  419. };
  421. thermal-zones {
  423. reserve_thermal {
  424. polling-delay-passive = < 0x3e8 >;
  425. polling-delay = < 0x1388 >;
  426. thermal-sensors = < 0x32 0x00 >;
  427. };
  429. cpu_thermal {
  430. polling-delay-passive = < 0x64 >;
  431. polling-delay = < 0x1388 >;
  432. thermal-sensors = < 0x32 0x01 >;
  434. trips {
  436. cpu_alert0 {
  437. temperature = < 0x11170 >;
  438. hysteresis = < 0x7d0 >;
  439. type = "passive";
  440. phandle = < 0x33 >;
  441. };
  443. cpu_alert1 {
  444. temperature = < 0x124f8 >;
  445. hysteresis = < 0x7d0 >;
  446. type = "passive";
  447. phandle = < 0x34 >;
  448. };
  450. cpu_crit {
  451. temperature = < 0x15f90 >;
  452. hysteresis = < 0x7d0 >;
  453. type = "critical";
  454. };
  455. };
  457. cooling-maps {
  459. map0 {
  460. trip = < 0x33 >;
  461. cooling-device = < 0x02 0xffffffff 0x06 >;
  462. };
  464. map1 {
  465. trip = < 0x34 >;
  466. cooling-device = < 0x02 0xffffffff 0xffffffff >;
  467. };
  468. };
  469. };
  471. gpu_thermal {
  472. polling-delay-passive = < 0x64 >;
  473. polling-delay = < 0x1388 >;
  474. thermal-sensors = < 0x32 0x02 >;
  476. trips {
  478. gpu_alert0 {
  479. temperature = < 0x11170 >;
  480. hysteresis = < 0x7d0 >;
  481. type = "passive";
  482. phandle = < 0x35 >;
  483. };
  485. gpu_crit {
  486. temperature = < 0x15f90 >;
  487. hysteresis = < 0x7d0 >;
  488. type = "critical";
  489. };
  490. };
  492. cooling-maps {
  494. map0 {
  495. trip = < 0x35 >;
  496. cooling-device = < 0x02 0xffffffff 0xffffffff >;
  497. };
  498. };
  499. };
  500. };
  502. tsadc@ff280000 {
  503. compatible = "rockchip,rk3288-tsadc";
  504. reg = < 0x00 0xff280000 0x00 0x100 >;
  505. interrupts = < 0x00 0x25 0x04 >;
  506. clocks = < 0x07 0x48 0x07 0x15a >;
  507. clock-names = "tsadc\0apb_pclk";
  508. resets = < 0x07 0x9f >;
  509. reset-names = "tsadc-apb";
  510. pinctrl-names = "init\0default\0sleep";
  511. pinctrl-0 = < 0x36 >;
  512. pinctrl-1 = < 0x37 >;
  513. pinctrl-2 = < 0x36 >;
  514. #thermal-sensor-cells = < 0x01 >;
  515. rockchip,hw-tshut-temp = < 0x17318 >;
  516. status = "okay";
  517. rockchip,hw-tshut-mode = < 0x01 >;
  518. rockchip,hw-tshut-polarity = < 0x01 >;
  519. phandle = < 0x32 >;
  520. };
  522. ethernet@ff290000 {
  523. compatible = "rockchip,rk3288-gmac";
  524. reg = < 0x00 0xff290000 0x00 0x10000 >;
  525. interrupts = < 0x00 0x1b 0x04 0x00 0x1c 0x04 >;
  526. interrupt-names = "macirq\0eth_wake_irq";
  527. rockchip,grf = < 0x38 >;
  528. clocks = < 0x07 0x97 0x07 0x66 0x07 0x67 0x07 0x63 0x07 0x98 0x07 0xc4 0x07 0x15d >;
  529. clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_ref\0clk_mac_refout\0aclk_mac\0pclk_mac";
  530. resets = < 0x07 0x42 >;
  531. reset-names = "stmmaceth";
  532. status = "ok";
  533. assigned-clocks = < 0x07 0x97 >;
  534. assigned-clock-parents = < 0x39 >;
  535. clock_in_out = "input";
  536. phy-mode = "rgmii";
  537. phy-supply = < 0x3a >;
  538. pinctrl-names = "default";
  539. pinctrl-0 = < 0x3b >;
  540. snps,reset-gpio = < 0x3c 0x07 0x00 >;
  541. snps,reset-active-low;
  542. snps,reset-delays-us = < 0x00 0x2710 0xf4240 >;
  543. tx_delay = < 0x30 >;
  544. rx_delay = < 0x10 >;
  545. };
  547. usb@ff500000 {
  548. compatible = "generic-ehci";
  549. reg = < 0x00 0xff500000 0x00 0x20000 >;
  550. interrupts = < 0x00 0x18 0x04 >;
  551. clocks = < 0x07 0x1c2 >;
  552. clock-names = "usbhost";
  553. phys = < 0x4e >;
  554. phy-names = "usb";
  555. status = "okay";
  556. no-relinquish-port;
  557. phandle = < 0xce >;
  558. };
  560. usb@ff520000 {
  561. compatible = "generic-ohci";
  562. reg = < 0x00 0xff520000 0x00 0x20000 >;
  563. interrupts = < 0x00 0x29 0x04 >;
  564. clocks = < 0x07 0x1c2 >;
  565. clock-names = "usbhost";
  566. phys = < 0x4e >;
  567. phy-names = "usb";
  568. status = "disabled";
  569. phandle = < 0xcf >;
  570. };
  572. usb@ff540000 {
  573. compatible = "rockchip,rk3288-usb\0rockchip,rk3066-usb\0snps,dwc2";
  574. reg = < 0x00 0xff540000 0x00 0x40000 >;
  575. interrupts = < 0x00 0x19 0x04 >;
  576. clocks = < 0x07 0x1c3 >;
  577. clock-names = "otg";
  578. dr_mode = "host";
  579. phys = < 0x4f >;
  580. phy-names = "usb2-phy";
  581. status = "okay";
  582. phandle = < 0xd0 >;
  583. };
  585. usb@ff580000 {
  586. compatible = "rockchip,rk3288-usb\0rockchip,rk3066-usb\0snps,dwc2";
  587. reg = < 0x00 0xff580000 0x00 0x40000 >;
  588. interrupts = < 0x00 0x17 0x04 >;
  589. clocks = < 0x07 0x1c1 >;
  590. clock-names = "otg";
  591. dr_mode = "otg";
  592. g-np-tx-fifo-size = < 0x10 >;
  593. g-rx-fifo-size = < 0x113 >;
  594. g-tx-fifo-size = < 0x100 0x80 0x80 0x40 0x40 0x20 >;
  595. g-use-dma;
  596. phys = < 0x50 >;
  597. phy-names = "usb2-phy";
  598. status = "okay";
  599. phandle = < 0xd1 >;
  600. };
  602. usb@ff5c0000 {
  603. compatible = "generic-ehci";
  604. reg = < 0x00 0xff5c0000 0x00 0x100 >;
  605. interrupts = < 0x00 0x1a 0x04 >;
  606. clocks = < 0x07 0x1c4 >;
  607. clock-names = "usbhost";
  608. status = "disabled";
  609. phandle = < 0xd2 >;
  610. };
  612. i2c@ff650000 {
  613. compatible = "rockchip,rk3288-i2c";
  614. reg = < 0x00 0xff650000 0x00 0x1000 >;
  615. interrupts = < 0x00 0x3c 0x04 >;
  616. #address-cells = < 0x01 >;
  617. #size-cells = < 0x00 >;
  618. clock-names = "i2c";
  619. clocks = < 0x07 0x14c >;
  620. pinctrl-names = "default";
  621. pinctrl-0 = < 0x40 >;
  622. status = "okay";
  623. clock-frequency = < 0x61a80 >;
  625. pmic@1b {
  626. compatible = "rockchip,rk808";
  627. reg = < 0x1b >;
  628. interrupt-parent = < 0x41 >;
  629. interrupts = < 0x04 0x08 >;
  630. #clock-cells = < 0x01 >;
  631. clock-output-names = "xin32k\0rk808-clkout2";
  632. dvs-gpios = < 0x41 0x0b 0x00 0x41 0x0c 0x00 >;
  633. pinctrl-names = "default";
  634. pinctrl-0 = < 0x42 0x43 0x44 0x45 >;
  635. rockchip,system-power-controller;
  636. wakeup-source;
  637. vcc1-supply = < 0x46 >;
  638. vcc2-supply = < 0x46 >;
  639. vcc3-supply = < 0x46 >;
  640. vcc4-supply = < 0x46 >;
  641. vcc6-supply = < 0x46 >;
  642. vcc7-supply = < 0x46 >;
  643. vcc8-supply = < 0x47 >;
  644. vcc9-supply = < 0x47 >;
  645. vcc10-supply = < 0x47 >;
  646. vcc11-supply = < 0x46 >;
  647. vcc12-supply = < 0x47 >;
  648. vddio-supply = < 0x47 >;
  649. phandle = < 0x80 >;
  651. regulators {
  653. DCDC_REG1 {
  654. regulator-always-on;
  655. regulator-boot-on;
  656. regulator-min-microvolt = < 0xb71b0 >;
  657. regulator-max-microvolt = < 0x149970 >;
  658. regulator-name = "vdd_arm";
  659. regulator-ramp-delay = < 0x1770 >;
  660. phandle = < 0x08 >;
  662. regulator-state-mem {
  663. regulator-off-in-suspend;
  664. };
  665. };
  667. DCDC_REG2 {
  668. regulator-always-on;
  669. regulator-boot-on;
  670. regulator-min-microvolt = < 0xcf850 >;
  671. regulator-max-microvolt = < 0x1312d0 >;
  672. regulator-name = "vdd_gpu";
  673. regulator-ramp-delay = < 0x1770 >;
  674. phandle = < 0x75 >;
  676. regulator-state-mem {
  677. regulator-on-in-suspend;
  678. regulator-suspend-microvolt = < 0xf4240 >;
  679. };
  680. };
  682. DCDC_REG3 {
  683. regulator-always-on;
  684. regulator-boot-on;
  685. regulator-name = "vcc_ddr";
  687. regulator-state-mem {
  688. regulator-on-in-suspend;
  689. };
  690. };
  692. DCDC_REG4 {
  693. regulator-always-on;
  694. regulator-boot-on;
  695. regulator-min-microvolt = < 0x325aa0 >;
  696. regulator-max-microvolt = < 0x325aa0 >;
  697. regulator-name = "vcc_io";
  698. phandle = < 0x47 >;
  700. regulator-state-mem {
  701. regulator-on-in-suspend;
  702. regulator-suspend-microvolt = < 0x325aa0 >;
  703. };
  704. };
  706. LDO_REG1 {
  707. regulator-always-on;
  708. regulator-boot-on;
  709. regulator-min-microvolt = < 0x1b7740 >;
  710. regulator-max-microvolt = < 0x1b7740 >;
  711. regulator-name = "vcc18_ldo1";
  712. phandle = < 0x1a >;
  714. regulator-state-mem {
  715. regulator-on-in-suspend;
  716. regulator-suspend-microvolt = < 0x1b7740 >;
  717. };
  718. };
  720. LDO_REG2 {
  721. regulator-always-on;
  722. regulator-boot-on;
  723. regulator-min-microvolt = < 0x325aa0 >;
  724. regulator-max-microvolt = < 0x325aa0 >;
  725. regulator-name = "vcc33_mipi";
  727. regulator-state-mem {
  728. regulator-off-in-suspend;
  729. };
  730. };
  732. LDO_REG3 {
  733. regulator-always-on;
  734. regulator-boot-on;
  735. regulator-min-microvolt = < 0xf4240 >;
  736. regulator-max-microvolt = < 0xf4240 >;
  737. regulator-name = "vdd_10";
  739. regulator-state-mem {
  740. regulator-on-in-suspend;
  741. regulator-suspend-microvolt = < 0xf4240 >;
  742. };
  743. };
  745. LDO_REG4 {
  746. regulator-always-on;
  747. regulator-boot-on;
  748. regulator-min-microvolt = < 0x1b7740 >;
  749. regulator-max-microvolt = < 0x1b7740 >;
  750. regulator-name = "vcc18_codec";
  752. regulator-state-mem {
  753. regulator-on-in-suspend;
  754. regulator-suspend-microvolt = < 0x1b7740 >;
  755. };
  756. };
  758. LDO_REG5 {
  759. regulator-min-microvolt = < 0x1b7740 >;
  760. regulator-max-microvolt = < 0x325aa0 >;
  761. regulator-name = "vccio_sd";
  762. phandle = < 0x11 >;
  764. regulator-state-mem {
  765. regulator-on-in-suspend;
  766. regulator-suspend-microvolt = < 0x325aa0 >;
  767. };
  768. };
  770. LDO_REG6 {
  771. regulator-always-on;
  772. regulator-boot-on;
  773. regulator-min-microvolt = < 0xf4240 >;
  774. regulator-max-microvolt = < 0xf4240 >;
  775. regulator-name = "vdd10_lcd";
  777. regulator-state-mem {
  778. regulator-on-in-suspend;
  779. regulator-suspend-microvolt = < 0xf4240 >;
  780. };
  781. };
  783. LDO_REG7 {
  784. regulator-always-on;
  785. regulator-boot-on;
  786. regulator-min-microvolt = < 0x1b7740 >;
  787. regulator-max-microvolt = < 0x1b7740 >;
  788. regulator-name = "vcc_18";
  789. phandle = < 0x7f >;
  791. regulator-state-mem {
  792. regulator-on-in-suspend;
  793. regulator-suspend-microvolt = < 0x1b7740 >;
  794. };
  795. };
  797. LDO_REG8 {
  798. regulator-always-on;
  799. regulator-boot-on;
  800. regulator-min-microvolt = < 0x1b7740 >;
  801. regulator-max-microvolt = < 0x1b7740 >;
  802. regulator-name = "vcc18_lcd";
  804. regulator-state-mem {
  805. regulator-on-in-suspend;
  806. regulator-suspend-microvolt = < 0x1b7740 >;
  807. };
  808. };
  810. SWITCH_REG1 {
  811. regulator-always-on;
  812. regulator-boot-on;
  813. regulator-name = "vcc33_sd";
  814. phandle = < 0x10 >;
  816. regulator-state-mem {
  817. regulator-on-in-suspend;
  818. };
  819. };
  821. SWITCH_REG2 {
  822. regulator-always-on;
  823. regulator-boot-on;
  824. regulator-name = "vcc33_lan";
  825. phandle = < 0x3a >;
  827. regulator-state-mem {
  828. regulator-on-in-suspend;
  829. };
  830. };
  831. };
  832. };
  833. };
  835. i2c@ff660000 {
  836. compatible = "rockchip,rk3288-i2c";
  837. reg = < 0x00 0xff660000 0x00 0x1000 >;
  838. interrupts = < 0x00 0x3d 0x04 >;
  839. #address-cells = < 0x01 >;
  840. #size-cells = < 0x00 >;
  841. clock-names = "i2c";
  842. clocks = < 0x07 0x14e >;
  843. pinctrl-names = "default";
  844. pinctrl-0 = < 0x48 >;
  845. status = "okay";
  846. };
  848. pwm@ff680000 {
  849. compatible = "rockchip,rk3288-pwm";
  850. reg = < 0x00 0xff680000 0x00 0x10 >;
  851. #pwm-cells = < 0x03 >;
  852. pinctrl-names = "default";
  853. pinctrl-0 = < 0x49 >;
  854. clocks = < 0x07 0x15e >;
  855. clock-names = "pwm";
  856. status = "okay";
  857. };
  859. pwm@ff680010 {
  860. compatible = "rockchip,rk3288-pwm";
  861. reg = < 0x00 0xff680010 0x00 0x10 >;
  862. #pwm-cells = < 0x03 >;
  863. pinctrl-names = "default";
  864. pinctrl-0 = < 0x4a >;
  865. clocks = < 0x07 0x15e >;
  866. clock-names = "pwm";
  867. status = "disabled";
  868. };
  870. pwm@ff680020 {
  871. compatible = "rockchip,rk3288-pwm";
  872. reg = < 0x00 0xff680020 0x00 0x10 >;
  873. #pwm-cells = < 0x03 >;
  874. pinctrl-names = "default";
  875. pinctrl-0 = < 0x4b >;
  876. clocks = < 0x07 0x15e >;
  877. clock-names = "pwm";
  878. status = "disabled";
  879. };
  881. pwm@ff680030 {
  882. compatible = "rockchip,rk3288-pwm";
  883. reg = < 0x00 0xff680030 0x00 0x10 >;
  884. #pwm-cells = < 0x02 >;
  885. pinctrl-names = "default";
  886. pinctrl-0 = < 0x4c >;
  887. clocks = < 0x07 0x15e >;
  888. clock-names = "pwm";
  889. status = "disabled";
  890. };
  892. bus_intmem@ff700000 {
  893. compatible = "mmio-sram";
  894. reg = < 0x00 0xff700000 0x00 0x18000 >;
  895. #address-cells = < 0x01 >;
  896. #size-cells = < 0x01 >;
  897. ranges = < 0x00 0x00 0xff700000 0x18000 >;
  899. smp-sram@0 {
  900. compatible = "rockchip,rk3066-smp-sram";
  901. reg = < 0x00 0x10 >;
  902. };
  903. };
  905. sram@ff720000 {
  906. compatible = "rockchip,rk3288-pmu-sram\0mmio-sram";
  907. reg = < 0x00 0xff720000 0x00 0x1000 >;
  908. };
  910. power-management@ff730000 {
  911. compatible = "rockchip,rk3288-pmu\0syscon\0simple-mfd";
  912. reg = < 0x00 0xff730000 0x00 0x100 >;
  913. phandle = < 0x06 >;
  915. power-controller {
  916. compatible = "rockchip,rk3288-power-controller";
  917. #power-domain-cells = < 0x01 >;
  918. #address-cells = < 0x01 >;
  919. #size-cells = < 0x00 >;
  920. assigned-clocks = < 0x07 0x68 >;
  921. assigned-clock-parents = < 0x09 >;
  922. phandle = < 0x5e >;
  924. pd_vio@9 {
  925. reg = < 0x09 >;
  926. clocks = < 0x07 0xca 0x07 0xcd 0x07 0xc8 0x07 0xcc 0x07 0xc5 0x07 0xc6 0x07 0xbe 0x07 0xbf 0x07 0x1d4 0x07 0x1d5 0x07 0x1d6 0x07 0x1d9 0x07 0x1d1 0x07 0x1d2 0x07 0x163 0x07 0x168 0x07 0x167 0x07 0x166 0x07 0x164 0x07 0x165 0x07 0x68 0x07 0x69 0x07 0x6c 0x07 0x6b 0x07 0x6a >;
  927. pm_qos = < 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 >;
  928. };
  930. pd_hevc@11 {
  931. reg = < 0x0b >;
  932. clocks = < 0x07 0xcf 0x07 0x6f 0x07 0x70 >;
  933. pm_qos = < 0x56 0x57 >;
  934. };
  936. pd_video@12 {
  937. reg = < 0x0c >;
  938. clocks = < 0x07 0xd0 0x07 0x1dc >;
  939. pm_qos = < 0x58 >;
  940. };
  942. pd_gpu@13 {
  943. reg = < 0x0d >;
  944. clocks = < 0x07 0xc0 >;
  945. pm_qos = < 0x59 0x5a >;
  946. };
  947. };
  949. reboot-mode {
  950. compatible = "syscon-reboot-mode";
  951. offset = < 0x94 >;
  952. mode-normal = < 0x5242c300 >;
  953. mode-recovery = < 0x5242c303 >;
  954. mode-bootloader = < 0x5242c309 >;
  955. mode-loader = < 0x5242c301 >;
  956. };
  957. };
  959. syscon@ff740000 {
  960. compatible = "rockchip,rk3288-sgrf\0syscon";
  961. reg = < 0x00 0xff740000 0x00 0x1000 >;
  962. };
  964. clock-controller@ff760000 {
  965. compatible = "rockchip,rk3288-cru";
  966. reg = < 0x00 0xff760000 0x00 0x1000 >;
  967. rockchip,grf = < 0x38 >;
  968. #clock-cells = < 0x01 >;
  969. #reset-cells = < 0x01 >;
  970. assigned-clocks = < 0x07 0x04 0x07 0x03 0x07 0x05 0x07 0xd1 0x07 0x1dd 0x07 0x16a 0x07 0xd2 0x07 0x1de 0x07 0x16b >;
  971. assigned-clock-rates = < 0x2367b880 0x17d78400 0x1dcd6500 0x11e1a300 0x8f0d180 0x47868c0 0x11e1a300 0x8f0d180 0x47868c0 >;
  972. phandle = < 0x07 >;
  973. };
  975. syscon@ff770000 {
  976. compatible = "rockchip,rk3288-grf\0syscon\0simple-mfd";
  977. reg = < 0x00 0xff770000 0x00 0x1000 >;
  978. phandle = < 0x38 >;
  980. edp-phy {
  981. compatible = "rockchip,rk3288-dp-phy";
  982. clocks = < 0x07 0x68 >;
  983. clock-names = "24m";
  984. #phy-cells = < 0x00 >;
  985. status = "disabled";
  986. phandle = < 0x6e >;
  987. };
  989. io-domains {
  990. compatible = "rockchip,rk3288-io-voltage-domain";
  991. status = "okay";
  992. sdcard-supply = < 0x11 >;
  993. };
  995. usbphy {
  996. compatible = "rockchip,rk3288-usb-phy";
  997. #address-cells = < 0x01 >;
  998. #size-cells = < 0x00 >;
  999. status = "okay";
  1001. usb-phy@320 {
  1002. #phy-cells = < 0x00 >;
  1003. reg = < 0x320 >;
  1004. clocks = < 0x07 0x5d >;
  1005. clock-names = "phyclk";
  1006. #clock-cells = < 0x00 >;
  1007. phandle = < 0x3f >;
  1008. };
  1010. usb-phy@334 {
  1011. #phy-cells = < 0x00 >;
  1012. reg = < 0x334 >;
  1013. clocks = < 0x07 0x5e >;
  1014. clock-names = "phyclk";
  1015. #clock-cells = < 0x00 >;
  1016. phandle = < 0x3d >;
  1017. };
  1019. usb-phy@348 {
  1020. #phy-cells = < 0x00 >;
  1021. reg = < 0x348 >;
  1022. clocks = < 0x07 0x5f >;
  1023. clock-names = "phyclk";
  1024. #clock-cells = < 0x00 >;
  1025. phandle = < 0x3e >;
  1026. };
  1027. };
  1028. };
  1030. watchdog@ff800000 {
  1031. compatible = "rockchip,rk3288-wdt\0snps,dw-wdt";
  1032. reg = < 0x00 0xff800000 0x00 0x100 >;
  1033. clocks = < 0x07 0x170 >;
  1034. interrupts = < 0x00 0x4f 0x04 >;
  1035. status = "okay";
  1036. };
  1038. sound@ff88b0000 {
  1039. compatible = "rockchip,rk3288-spdif\0rockchip,rk3066-spdif";
  1040. reg = < 0x00 0xff8b0000 0x00 0x10000 >;
  1041. #sound-dai-cells = < 0x00 >;
  1042. clock-names = "hclk\0mclk";
  1043. clocks = < 0x07 0x1d0 0x07 0x54 >;
  1044. dmas = < 0x5b 0x03 >;
  1045. dma-names = "tx";
  1046. interrupts = < 0x00 0x36 0x04 >;
  1047. pinctrl-names = "default";
  1048. pinctrl-0 = < 0x5c >;
  1049. rockchip,grf = < 0x38 >;
  1050. status = "disabled";
  1051. };
  1053. i2s@ff890000 {
  1054. compatible = "rockchip,rk3288-i2s\0rockchip,rk3066-i2s";
  1055. reg = < 0x00 0xff890000 0x00 0x10000 >;
  1056. #sound-dai-cells = < 0x00 >;
  1057. interrupts = < 0x00 0x35 0x04 >;
  1058. #address-cells = < 0x01 >;
  1059. #size-cells = < 0x00 >;
  1060. dmas = < 0x5b 0x00 0x5b 0x01 >;
  1061. dma-names = "tx\0rx";
  1062. clock-names = "i2s_hclk\0i2s_clk";
  1063. clocks = < 0x07 0x1ce 0x07 0x52 >;
  1064. pinctrl-names = "default";
  1065. pinctrl-0 = < 0x5d >;
  1066. rockchip,playback-channels = < 0x08 >;
  1067. rockchip,capture-channels = < 0x02 >;
  1068. status = "okay";
  1069. phandle = < 0x86 >;
  1070. };
  1072. cypto-controller@ff8a0000 {
  1073. compatible = "rockchip,rk3288-crypto";
  1074. reg = < 0x00 0xff8a0000 0x00 0x4000 >;
  1075. interrupts = < 0x00 0x30 0x04 >;
  1076. clocks = < 0x07 0xc7 0x07 0x1cd 0x07 0x7d 0x07 0xc1 >;
  1077. clock-names = "aclk\0hclk\0sclk\0apb_pclk";
  1078. resets = < 0x07 0xae >;
  1079. reset-names = "crypto-rst";
  1080. status = "okay";
  1081. };
  1083. iommu@ff900800 {
  1084. compatible = "rockchip,iommu";
  1085. reg = < 0x00 0xff900800 0x00 0x40 >;
  1086. interrupts = < 0x00 0x11 0x04 >;
  1087. interrupt-names = "iep_mmu";
  1088. #iommu-cells = < 0x00 >;
  1089. status = "disabled";
  1090. };
  1092. iommu@ff914000 {
  1093. compatible = "rockchip,iommu";
  1094. reg = < 0x00 0xff914000 0x00 0x100 0x00 0xff915000 0x00 0x100 >;
  1095. interrupts = < 0x00 0x0e 0x04 >;
  1096. interrupt-names = "isp_mmu";
  1097. #iommu-cells = < 0x00 >;
  1098. rockchip,disable-mmu-reset;
  1099. status = "disabled";
  1100. };
  1102. rga@ff920000 {
  1103. compatible = "rockchip,rk3288-rga";
  1104. reg = < 0x00 0xff920000 0x00 0x180 >;
  1105. interrupts = < 0x00 0x12 0x04 >;
  1106. clocks = < 0x07 0xc8 0x07 0x1d6 0x07 0x6a >;
  1107. clock-names = "aclk\0hclk\0sclk";
  1108. power-domains = < 0x5e 0x09 >;
  1109. resets = < 0x07 0x69 0x07 0x6c 0x07 0x6d >;
  1110. reset-names = "core\0axi\0ahb";
  1111. };
  1113. vop@ff930000 {
  1114. compatible = "rockchip,rk3288-vop";
  1115. reg = < 0x00 0xff930000 0x00 0x19c >;
  1116. interrupts = < 0x00 0x0f 0x04 >;
  1117. clocks = < 0x07 0xc5 0x07 0xbe 0x07 0x1d1 >;
  1118. clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
  1119. power-domains = < 0x5e 0x09 >;
  1120. resets = < 0x07 0x64 0x07 0x65 0x07 0x66 >;
  1121. reset-names = "axi\0ahb\0dclk";
  1122. iommus = < 0x5f >;
  1123. status = "okay";
  1125. port {
  1126. #address-cells = < 0x01 >;
  1127. #size-cells = < 0x00 >;
  1128. phandle = < 0x0b >;
  1130. endpoint@0 {
  1131. reg = < 0x00 >;
  1132. remote-endpoint = < 0x60 >;
  1133. phandle = < 0x72 >;
  1134. };
  1136. endpoint@1 {
  1137. reg = < 0x01 >;
  1138. remote-endpoint = < 0x61 >;
  1139. phandle = < 0x6f >;
  1140. };
  1142. endpoint@2 {
  1143. reg = < 0x02 >;
  1144. remote-endpoint = < 0x62 >;
  1145. phandle = < 0x69 >;
  1146. };
  1148. endpoint@3 {
  1149. reg = < 0x03 >;
  1150. remote-endpoint = < 0x63 >;
  1151. phandle = < 0x6c >;
  1152. };
  1153. };
  1154. };
  1156. iommu@ff930300 {
  1157. compatible = "rockchip,iommu";
  1158. reg = < 0x00 0xff930300 0x00 0x100 >;
  1159. interrupts = < 0x00 0x0f 0x04 >;
  1160. interrupt-names = "vopb_mmu";
  1161. power-domains = < 0x5e 0x09 >;
  1162. #iommu-cells = < 0x00 >;
  1163. status = "okay";
  1164. phandle = < 0x5f >;
  1165. };
  1167. vop@ff940000 {
  1168. compatible = "rockchip,rk3288-vop";
  1169. reg = < 0x00 0xff940000 0x00 0x19c >;
  1170. interrupts = < 0x00 0x10 0x04 >;
  1171. clocks = < 0x07 0xc6 0x07 0xbf 0x07 0x1d2 >;
  1172. clock-names = "aclk_vop\0dclk_vop\0hclk_vop";
  1173. power-domains = < 0x5e 0x09 >;
  1174. resets = < 0x07 0xb0 0x07 0xb1 0x07 0xb2 >;
  1175. reset-names = "axi\0ahb\0dclk";
  1176. iommus = < 0x64 >;
  1177. status = "okay";
  1179. port {
  1180. #address-cells = < 0x01 >;
  1181. #size-cells = < 0x00 >;
  1182. phandle = < 0x0a >;
  1184. endpoint@0 {
  1185. reg = < 0x00 >;
  1186. remote-endpoint = < 0x65 >;
  1187. phandle = < 0x73 >;
  1188. };
  1190. endpoint@1 {
  1191. reg = < 0x01 >;
  1192. remote-endpoint = < 0x66 >;
  1193. phandle = < 0x70 >;
  1194. };
  1196. endpoint@2 {
  1197. reg = < 0x02 >;
  1198. remote-endpoint = < 0x67 >;
  1199. phandle = < 0x6a >;
  1200. };
  1202. endpoint@3 {
  1203. reg = < 0x03 >;
  1204. remote-endpoint = < 0x68 >;
  1205. phandle = < 0x6d >;
  1206. };
  1207. };
  1208. };
  1210. iommu@ff940300 {
  1211. compatible = "rockchip,iommu";
  1212. reg = < 0x00 0xff940300 0x00 0x100 >;
  1213. interrupts = < 0x00 0x10 0x04 >;
  1214. interrupt-names = "vopl_mmu";
  1215. power-domains = < 0x5e 0x09 >;
  1216. #iommu-cells = < 0x00 >;
  1217. status = "okay";
  1218. phandle = < 0x64 >;
  1219. };
  1221. mipi@ff960000 {
  1222. compatible = "rockchip,rk3288-mipi-dsi\0snps,dw-mipi-dsi";
  1223. reg = < 0x00 0xff960000 0x00 0x4000 >;
  1224. interrupts = < 0x00 0x13 0x04 >;
  1225. clocks = < 0x07 0x7e 0x07 0x164 >;
  1226. clock-names = "ref\0pclk";
  1227. power-domains = < 0x5e 0x09 >;
  1228. rockchip,grf = < 0x38 >;
  1229. #address-cells = < 0x01 >;
  1230. #size-cells = < 0x00 >;
  1231. status = "disabled";
  1233. ports {
  1235. port {
  1236. #address-cells = < 0x01 >;
  1237. #size-cells = < 0x00 >;
  1239. endpoint@0 {
  1240. reg = < 0x00 >;
  1241. remote-endpoint = < 0x69 >;
  1242. phandle = < 0x62 >;
  1243. };
  1245. endpoint@1 {
  1246. reg = < 0x01 >;
  1247. remote-endpoint = < 0x6a >;
  1248. phandle = < 0x67 >;
  1249. };
  1250. };
  1251. };
  1252. };
  1254. lvds@ff96c000 {
  1255. compatible = "rockchip,rk3288-lvds";
  1256. reg = < 0x00 0xff96c000 0x00 0x4000 >;
  1257. clocks = < 0x07 0x167 >;
  1258. clock-names = "pclk_lvds";
  1259. pinctrl-names = "lcdc";
  1260. pinctrl-0 = < 0x6b >;
  1261. power-domains = < 0x5e 0x09 >;
  1262. rockchip,grf = < 0x38 >;
  1263. status = "disabled";
  1265. ports {
  1266. #address-cells = < 0x01 >;
  1267. #size-cells = < 0x00 >;
  1269. port@0 {
  1270. reg = < 0x00 >;
  1271. #address-cells = < 0x01 >;
  1272. #size-cells = < 0x00 >;
  1274. endpoint@0 {
  1275. reg = < 0x00 >;
  1276. remote-endpoint = < 0x6c >;
  1277. phandle = < 0x63 >;
  1278. };
  1280. endpoint@1 {
  1281. reg = < 0x01 >;
  1282. remote-endpoint = < 0x6d >;
  1283. phandle = < 0x68 >;
  1284. };
  1285. };
  1286. };
  1287. };
  1289. dp@ff970000 {
  1290. compatible = "rockchip,rk3288-dp";
  1291. reg = < 0x00 0xff970000 0x00 0x4000 >;
  1292. interrupts = < 0x00 0x62 0x04 >;
  1293. clocks = < 0x07 0x69 0x07 0x163 >;
  1294. clock-names = "dp\0pclk";
  1295. phys = < 0x6e >;
  1296. phy-names = "dp";
  1297. resets = < 0x07 0x6f >;
  1298. reset-names = "dp";
  1299. rockchip,grf = < 0x38 >;
  1300. status = "disabled";
  1302. ports {
  1303. #address-cells = < 0x01 >;
  1304. #size-cells = < 0x00 >;
  1306. port@0 {
  1307. reg = < 0x00 >;
  1308. #address-cells = < 0x01 >;
  1309. #size-cells = < 0x00 >;
  1311. endpoint@0 {
  1312. reg = < 0x00 >;
  1313. remote-endpoint = < 0x6f >;
  1314. phandle = < 0x61 >;
  1315. };
  1317. endpoint@1 {
  1318. reg = < 0x01 >;
  1319. remote-endpoint = < 0x70 >;
  1320. phandle = < 0x66 >;
  1321. };
  1322. };
  1323. };
  1324. };
  1326. hdmi@ff980000 {
  1327. compatible = "rockchip,rk3288-dw-hdmi";
  1328. reg = < 0x00 0xff980000 0x00 0x20000 >;
  1329. reg-io-width = < 0x04 >;
  1330. #sound-dai-cells = < 0x00 >;
  1331. rockchip,grf = < 0x38 >;
  1332. interrupts = < 0x00 0x67 0x04 >;
  1333. clocks = < 0x07 0x168 0x07 0x6d 0x07 0x6e >;
  1334. clock-names = "iahb\0isfr\0cec";
  1335. power-domains = < 0x5e 0x09 >;
  1336. status = "okay";
  1337. ddc-i2c-bus = < 0x71 >;
  1338. phandle = < 0x85 >;
  1340. ports {
  1342. port {
  1343. #address-cells = < 0x01 >;
  1344. #size-cells = < 0x00 >;
  1346. endpoint@0 {
  1347. reg = < 0x00 >;
  1348. remote-endpoint = < 0x72 >;
  1349. phandle = < 0x60 >;
  1350. };
  1352. endpoint@1 {
  1353. reg = < 0x01 >;
  1354. remote-endpoint = < 0x73 >;
  1355. phandle = < 0x65 >;
  1356. };
  1357. };
  1358. };
  1359. };
  1361. iommu@ff9a0800 {
  1362. compatible = "rockchip,iommu";
  1363. reg = < 0x00 0xff9a0800 0x00 0x100 >;
  1364. interrupts = < 0x00 0x0b 0x04 >;
  1365. interrupt-names = "vpu_mmu";
  1366. #iommu-cells = < 0x00 >;
  1367. status = "disabled";
  1368. };
  1370. iommu@ff9c0440 {
  1371. compatible = "rockchip,iommu";
  1372. reg = < 0x00 0xff9c0440 0x00 0x40 0x00 0xff9c0480 0x00 0x40 >;
  1373. interrupts = < 0x00 0x6f 0x04 >;
  1374. interrupt-names = "hevc_mmu";
  1375. #iommu-cells = < 0x00 >;
  1376. status = "disabled";
  1377. };
  1379. gpu@ffa30000 {
  1380. compatible = "rockchip,rk3288-mali\0arm,mali-t760";
  1381. reg = < 0x00 0xffa30000 0x00 0x10000 >;
  1382. interrupts = < 0x00 0x06 0x04 0x00 0x07 0x04 0x00 0x08 0x04 >;
  1383. interrupt-names = "job\0mmu\0gpu";
  1384. clocks = < 0x07 0xc0 >;
  1385. operating-points-v2 = < 0x74 >;
  1386. power-domains = < 0x5e 0x0d >;
  1387. status = "okay";
  1388. mali-supply = < 0x75 >;
  1389. };
  1391. gpu-opp-table {
  1392. compatible = "operating-points-v2";
  1393. phandle = < 0x74 >;
  1395. opp@100000000 {
  1396. opp-hz = < 0x00 0x5f5e100 >;
  1397. opp-microvolt = < 0xe7ef0 >;
  1398. };
  1400. opp@200000000 {
  1401. opp-hz = < 0x00 0xbebc200 >;
  1402. opp-microvolt = < 0xe7ef0 >;
  1403. };
  1405. opp@300000000 {
  1406. opp-hz = < 0x00 0x11e1a300 >;
  1407. opp-microvolt = < 0xf4240 >;
  1408. };
  1410. opp@400000000 {
  1411. opp-hz = < 0x00 0x17d78400 >;
  1412. opp-microvolt = < 0x10c8e0 >;
  1413. };
  1415. opp@500000000 {
  1416. opp-hz = < 0x00 0x1dcd6500 >;
  1417. opp-microvolt = < 0x124f80 >;
  1418. };
  1420. opp@600000000 {
  1421. opp-hz = < 0x00 0x23c34600 >;
  1422. opp-microvolt = < 0x1312d0 >;
  1423. };
  1424. };
  1426. qos@ffaa0000 {
  1427. compatible = "syscon";
  1428. reg = < 0x00 0xffaa0000 0x00 0x20 >;
  1429. phandle = < 0x59 >;
  1430. };
  1432. qos@ffaa0080 {
  1433. compatible = "syscon";
  1434. reg = < 0x00 0xffaa0080 0x00 0x20 >;
  1435. phandle = < 0x5a >;
  1436. };
  1438. qos@ffad0000 {
  1439. compatible = "syscon";
  1440. reg = < 0x00 0xffad0000 0x00 0x20 >;
  1441. phandle = < 0x4e >;
  1442. };
  1444. qos@ffad0100 {
  1445. compatible = "syscon";
  1446. reg = < 0x00 0xffad0100 0x00 0x20 >;
  1447. phandle = < 0x4f >;
  1448. };
  1450. qos@ffad0180 {
  1451. compatible = "syscon";
  1452. reg = < 0x00 0xffad0180 0x00 0x20 >;
  1453. phandle = < 0x50 >;
  1454. };
  1456. qos@ffad0400 {
  1457. compatible = "syscon";
  1458. reg = < 0x00 0xffad0400 0x00 0x20 >;
  1459. phandle = < 0x51 >;
  1460. };
  1462. qos@ffad0480 {
  1463. compatible = "syscon";
  1464. reg = < 0x00 0xffad0480 0x00 0x20 >;
  1465. phandle = < 0x52 >;
  1466. };
  1468. qos@ffad0500 {
  1469. compatible = "syscon";
  1470. reg = < 0x00 0xffad0500 0x00 0x20 >;
  1471. phandle = < 0x4d >;
  1472. };
  1474. qos@ffad0800 {
  1475. compatible = "syscon";
  1476. reg = < 0x00 0xffad0800 0x00 0x20 >;
  1477. phandle = < 0x53 >;
  1478. };
  1480. qos@ffad0880 {
  1481. compatible = "syscon";
  1482. reg = < 0x00 0xffad0880 0x00 0x20 >;
  1483. phandle = < 0x54 >;
  1484. };
  1486. qos@ffad0900 {
  1487. compatible = "syscon";
  1488. reg = < 0x00 0xffad0900 0x00 0x20 >;
  1489. phandle = < 0x55 >;
  1490. };
  1492. qos@ffae0000 {
  1493. compatible = "syscon";
  1494. reg = < 0x00 0xffae0000 0x00 0x20 >;
  1495. phandle = < 0x58 >;
  1496. };
  1498. qos@ffaf0000 {
  1499. compatible = "syscon";
  1500. reg = < 0x00 0xffaf0000 0x00 0x20 >;
  1501. phandle = < 0x56 >;
  1502. };
  1504. qos@ffaf0080 {
  1505. compatible = "syscon";
  1506. reg = < 0x00 0xffaf0080 0x00 0x20 >;
  1507. phandle = < 0x57 >;
  1508. };
  1510. interrupt-controller@ffc01000 {
  1511. compatible = "arm,gic-400";
  1512. interrupt-controller;
  1513. #interrupt-cells = < 0x03 >;
  1514. #address-cells = < 0x00 >;
  1515. reg = < 0x00 0xffc01000 0x00 0x1000 0x00 0xffc02000 0x00 0x2000 0x00 0xffc04000 0x00 0x2000 0x00 0xffc06000 0x00 0x2000 >;
  1516. interrupts = < 0x01 0x09 0xf04 >;
  1517. phandle = < 0x01 >;
  1518. };
  1520. efuse@ffb40000 {
  1521. compatible = "rockchip,rk3288-efuse";
  1522. reg = < 0x00 0xffb40000 0x00 0x20 >;
  1523. #address-cells = < 0x01 >;
  1524. #size-cells = < 0x01 >;
  1525. clocks = < 0x07 0x171 >;
  1526. clock-names = "pclk_efuse";
  1528. cpu_leakage@17 {
  1529. reg = < 0x17 0x01 >;
  1530. };
  1531. };
  1533. pinctrl {
  1534. compatible = "rockchip,rk3288-pinctrl";
  1535. rockchip,grf = < 0x38 >;
  1536. rockchip,pmu = < 0x06 >;
  1537. #address-cells = < 0x02 >;
  1538. #size-cells = < 0x02 >;
  1539. ranges;
  1541. gpio0@ff750000 {
  1542. compatible = "rockchip,gpio-bank";
  1543. reg = < 0x00 0xff750000 0x00 0x100 >;
  1544. interrupts = < 0x00 0x51 0x04 >;
  1545. clocks = < 0x07 0x140 >;
  1546. gpio-controller;
  1547. #gpio-cells = < 0x02 >;
  1548. interrupt-controller;
  1549. #interrupt-cells = < 0x02 >;
  1550. phandle = < 0x41 >;
  1551. };
  1553. gpio1@ff780000 {
  1554. compatible = "rockchip,gpio-bank";
  1555. reg = < 0x00 0xff780000 0x00 0x100 >;
  1556. interrupts = < 0x00 0x52 0x04 >;
  1557. clocks = < 0x07 0x141 >;
  1558. gpio-controller;
  1559. #gpio-cells = < 0x02 >;
  1560. interrupt-controller;
  1561. #interrupt-cells = < 0x02 >;
  1562. phandle = < 0x84 >;
  1563. };
  1565. gpio2@ff790000 {
  1566. compatible = "rockchip,gpio-bank";
  1567. reg = < 0x00 0xff790000 0x00 0x100 >;
  1568. interrupts = < 0x00 0x53 0x04 >;
  1569. clocks = < 0x07 0x142 >;
  1570. gpio-controller;
  1571. #gpio-cells = < 0x02 >;
  1572. interrupt-controller;
  1573. #interrupt-cells = < 0x02 >;
  1574. };
  1576. gpio3@ff7a0000 {
  1577. compatible = "rockchip,gpio-bank";
  1578. reg = < 0x00 0xff7a0000 0x00 0x100 >;
  1579. interrupts = < 0x00 0x54 0x04 >;
  1580. clocks = < 0x07 0x143 >;
  1581. gpio-controller;
  1582. #gpio-cells = < 0x02 >;
  1583. interrupt-controller;
  1584. #interrupt-cells = < 0x02 >;
  1585. };
  1587. gpio4@ff7b0000 {
  1588. compatible = "rockchip,gpio-bank";
  1589. reg = < 0x00 0xff7b0000 0x00 0x100 >;
  1590. interrupts = < 0x00 0x55 0x04 >;
  1591. clocks = < 0x07 0x144 >;
  1592. gpio-controller;
  1593. #gpio-cells = < 0x02 >;
  1594. interrupt-controller;
  1595. #interrupt-cells = < 0x02 >;
  1596. phandle = < 0x3c >;
  1597. };
  1599. gpio5@ff7c0000 {
  1600. compatible = "rockchip,gpio-bank";
  1601. reg = < 0x00 0xff7c0000 0x00 0x100 >;
  1602. interrupts = < 0x00 0x56 0x04 >;
  1603. clocks = < 0x07 0x145 >;
  1604. gpio-controller;
  1605. #gpio-cells = < 0x02 >;
  1606. interrupt-controller;
  1607. #interrupt-cells = < 0x02 >;
  1608. };
  1610. gpio6@ff7d0000 {
  1611. compatible = "rockchip,gpio-bank";
  1612. reg = < 0x00 0xff7d0000 0x00 0x100 >;
  1613. interrupts = < 0x00 0x57 0x04 >;
  1614. clocks = < 0x07 0x146 >;
  1615. gpio-controller;
  1616. #gpio-cells = < 0x02 >;
  1617. interrupt-controller;
  1618. #interrupt-cells = < 0x02 >;
  1619. };
  1621. gpio7@ff7e0000 {
  1622. compatible = "rockchip,gpio-bank";
  1623. reg = < 0x00 0xff7e0000 0x00 0x100 >;
  1624. interrupts = < 0x00 0x58 0x04 >;
  1625. clocks = < 0x07 0x147 >;
  1626. gpio-controller;
  1627. #gpio-cells = < 0x02 >;
  1628. interrupt-controller;
  1629. #interrupt-cells = < 0x02 >;
  1630. phandle = < 0x87 >;
  1631. };
  1633. gpio8@ff7f0000 {
  1634. compatible = "rockchip,gpio-bank";
  1635. reg = < 0x00 0xff7f0000 0x00 0x100 >;
  1636. interrupts = < 0x00 0x59 0x04 >;
  1637. clocks = < 0x07 0x148 >;
  1638. gpio-controller;
  1639. #gpio-cells = < 0x02 >;
  1640. interrupt-controller;
  1641. #interrupt-cells = < 0x02 >;
  1642. };
  1644. hdmi {
  1646. hdmi-cec-c0 {
  1647. rockchip,pins = < 0x07 0x10 0x02 0x76 >;
  1648. };
  1650. hdmi-cec-c7 {
  1651. rockchip,pins = < 0x07 0x17 0x04 0x76 >;
  1652. };
  1654. hdmi-ddc {
  1655. rockchip,pins = < 0x07 0x13 0x02 0x76 0x07 0x14 0x02 0x76 >;
  1656. };
  1657. };
  1659. pcfg-pull-up {
  1660. bias-pull-up;
  1661. phandle = < 0x77 >;
  1662. };
  1664. pcfg-pull-down {
  1665. bias-pull-down;
  1666. phandle = < 0x78 >;
  1667. };
  1669. pcfg-pull-none {
  1670. bias-disable;
  1671. phandle = < 0x76 >;
  1672. };
  1674. pcfg-pull-none-12ma {
  1675. bias-disable;
  1676. drive-strength = < 0x0c >;
  1677. phandle = < 0x7b >;
  1678. };
  1680. sleep {
  1682. global-pwroff {
  1683. rockchip,pins = < 0x00 0x00 0x01 0x76 >;
  1684. phandle = < 0x43 >;
  1685. };
  1687. ddrio-pwroff {
  1688. rockchip,pins = < 0x00 0x01 0x01 0x76 >;
  1689. };
  1691. ddr0-retention {
  1692. rockchip,pins = < 0x00 0x02 0x01 0x77 >;
  1693. };
  1695. ddr1-retention {
  1696. rockchip,pins = < 0x00 0x03 0x01 0x77 >;
  1697. };
  1698. };
  1700. edp {
  1702. edp-hpd {
  1703. rockchip,pins = < 0x07 0x0b 0x02 0x78 >;
  1704. };
  1705. };
  1707. i2c0 {
  1709. i2c0-xfer {
  1710. rockchip,pins = < 0x00 0x0f 0x01 0x76 0x00 0x10 0x01 0x76 >;
  1711. phandle = < 0x40 >;
  1712. };
  1713. };
  1715. i2c1 {
  1717. i2c1-xfer {
  1718. rockchip,pins = < 0x08 0x04 0x01 0x76 0x08 0x05 0x01 0x76 >;
  1719. phandle = < 0x28 >;
  1720. };
  1721. };
  1723. i2c2 {
  1725. i2c2-xfer {
  1726. rockchip,pins = < 0x06 0x09 0x01 0x76 0x06 0x0a 0x01 0x76 >;
  1727. phandle = < 0x48 >;
  1728. };
  1729. };
  1731. i2c3 {
  1733. i2c3-xfer {
  1734. rockchip,pins = < 0x02 0x10 0x01 0x76 0x02 0x11 0x01 0x76 >;
  1735. phandle = < 0x29 >;
  1736. };
  1737. };
  1739. i2c4 {
  1741. i2c4-xfer {
  1742. rockchip,pins = < 0x07 0x11 0x01 0x76 0x07 0x12 0x01 0x76 >;
  1743. phandle = < 0x2a >;
  1744. };
  1745. };
  1747. i2c5 {
  1749. i2c5-xfer {
  1750. rockchip,pins = < 0x07 0x13 0x01 0x76 0x07 0x14 0x01 0x76 >;
  1751. phandle = < 0x2b >;
  1752. };
  1753. };
  1755. i2s0 {
  1757. i2s0-bus {
  1758. rockchip,pins = < 0x06 0x00 0x01 0x76 0x06 0x01 0x01 0x76 0x06 0x02 0x01 0x76 0x06 0x03 0x01 0x76 0x06 0x04 0x01 0x76 0x06 0x08 0x01 0x76 >;
  1759. phandle = < 0x5d >;
  1760. };
  1761. };
  1763. lcdc {
  1765. lcdc-ctl {
  1766. rockchip,pins = < 0x01 0x18 0x01 0x76 0x01 0x19 0x01 0x76 0x01 0x1a 0x01 0x76 0x01 0x1b 0x01 0x76 >;
  1767. phandle = < 0x6b >;
  1768. };
  1769. };
  1771. sdmmc {
  1773. sdmmc-clk {
  1774. rockchip,pins = < 0x06 0x14 0x01 0x79 >;
  1775. phandle = < 0x0c >;
  1776. };
  1778. sdmmc-cmd {
  1779. rockchip,pins = < 0x06 0x15 0x01 0x7a >;
  1780. phandle = < 0x0d >;
  1781. };
  1783. sdmmc-cd {
  1784. rockchip,pins = < 0x06 0x16 0x01 0x77 >;
  1785. phandle = < 0x0e >;
  1786. };
  1788. sdmmc-bus1 {
  1789. rockchip,pins = < 0x06 0x10 0x01 0x77 >;
  1790. };
  1792. sdmmc-bus4 {
  1793. rockchip,pins = < 0x06 0x10 0x01 0x7a 0x06 0x11 0x01 0x7a 0x06 0x12 0x01 0x7a 0x06 0x13 0x01 0x7a >;
  1794. phandle = < 0x0f >;
  1795. };
  1797. sdmmc-pwr {
  1798. rockchip,pins = < 0x07 0x0b 0x00 0x76 >;
  1799. phandle = < 0x88 >;
  1800. };
  1801. };
  1803. sdio0 {
  1805. sdio0-bus1 {
  1806. rockchip,pins = < 0x04 0x14 0x01 0x77 >;
  1807. };
  1809. sdio0-bus4 {
  1810. rockchip,pins = < 0x04 0x14 0x01 0x77 0x04 0x15 0x01 0x77 0x04 0x16 0x01 0x77 0x04 0x17 0x01 0x77 >;
  1811. phandle = < 0x13 >;
  1812. };
  1814. sdio0-cmd {
  1815. rockchip,pins = < 0x04 0x18 0x01 0x77 >;
  1816. phandle = < 0x14 >;
  1817. };
  1819. sdio0-clk {
  1820. rockchip,pins = < 0x04 0x19 0x01 0x76 >;
  1821. phandle = < 0x15 >;
  1822. };
  1824. sdio0-cd {
  1825. rockchip,pins = < 0x04 0x1a 0x01 0x77 >;
  1826. };
  1828. sdio0-wp {
  1829. rockchip,pins = < 0x04 0x1b 0x01 0x77 >;
  1830. };
  1832. sdio0-pwr {
  1833. rockchip,pins = < 0x04 0x1c 0x01 0x77 >;
  1834. };
  1836. sdio0-bkpwr {
  1837. rockchip,pins = < 0x04 0x1d 0x01 0x77 >;
  1838. };
  1840. sdio0-int {
  1841. rockchip,pins = < 0x04 0x1e 0x01 0x77 >;
  1842. };
  1843. };
  1845. sdio1 {
  1847. sdio1-bus1 {
  1848. rockchip,pins = < 0x03 0x18 0x04 0x77 >;
  1849. };
  1851. sdio1-bus4 {
  1852. rockchip,pins = < 0x03 0x18 0x04 0x77 0x03 0x19 0x04 0x77 0x03 0x1a 0x04 0x77 0x03 0x1b 0x04 0x77 >;
  1853. };
  1855. sdio1-cd {
  1856. rockchip,pins = < 0x03 0x1c 0x04 0x77 >;
  1857. };
  1859. sdio1-wp {
  1860. rockchip,pins = < 0x03 0x1d 0x04 0x77 >;
  1861. };
  1863. sdio1-bkpwr {
  1864. rockchip,pins = < 0x03 0x1e 0x04 0x77 >;
  1865. };
  1867. sdio1-int {
  1868. rockchip,pins = < 0x03 0x1f 0x04 0x77 >;
  1869. };
  1871. sdio1-cmd {
  1872. rockchip,pins = < 0x04 0x06 0x04 0x77 >;
  1873. };
  1875. sdio1-clk {
  1876. rockchip,pins = < 0x04 0x07 0x04 0x76 >;
  1877. };
  1879. sdio1-pwr {
  1880. rockchip,pins = < 0x04 0x09 0x04 0x77 >;
  1881. };
  1882. };
  1884. emmc {
  1886. emmc-clk {
  1887. rockchip,pins = < 0x03 0x12 0x02 0x76 >;
  1888. phandle = < 0x16 >;
  1889. };
  1891. emmc-cmd {
  1892. rockchip,pins = < 0x03 0x10 0x02 0x77 >;
  1893. phandle = < 0x17 >;
  1894. };
  1896. emmc-pwr {
  1897. rockchip,pins = < 0x03 0x09 0x02 0x77 >;
  1898. phandle = < 0x18 >;
  1899. };
  1901. emmc-bus1 {
  1902. rockchip,pins = < 0x03 0x00 0x02 0x77 >;
  1903. };
  1905. emmc-bus4 {
  1906. rockchip,pins = < 0x03 0x00 0x02 0x77 0x03 0x01 0x02 0x77 0x03 0x02 0x02 0x77 0x03 0x03 0x02 0x77 >;
  1907. };
  1909. emmc-bus8 {
  1910. rockchip,pins = < 0x03 0x00 0x02 0x77 0x03 0x01 0x02 0x77 0x03 0x02 0x02 0x77 0x03 0x03 0x02 0x77 0x03 0x04 0x02 0x77 0x03 0x05 0x02 0x77 0x03 0x06 0x02 0x77 0x03 0x07 0x02 0x77 >;
  1911. phandle = < 0x19 >;
  1912. };
  1913. };
  1915. spi0 {
  1917. spi0-clk {
  1918. rockchip,pins = < 0x05 0x0c 0x01 0x77 >;
  1919. phandle = < 0x1c >;
  1920. };
  1922. spi0-cs0 {
  1923. rockchip,pins = < 0x05 0x0d 0x01 0x77 >;
  1924. phandle = < 0x1f >;
  1925. };
  1927. spi0-tx {
  1928. rockchip,pins = < 0x05 0x0e 0x01 0x77 >;
  1929. phandle = < 0x1d >;
  1930. };
  1932. spi0-rx {
  1933. rockchip,pins = < 0x05 0x0f 0x01 0x77 >;
  1934. phandle = < 0x1e >;
  1935. };
  1937. spi0-cs1 {
  1938. rockchip,pins = < 0x05 0x10 0x01 0x77 >;
  1939. };
  1940. };
  1942. spi1 {
  1944. spi1-clk {
  1945. rockchip,pins = < 0x07 0x0c 0x02 0x77 >;
  1946. phandle = < 0x20 >;
  1947. };
  1949. spi1-cs0 {
  1950. rockchip,pins = < 0x07 0x0d 0x02 0x77 >;
  1951. phandle = < 0x23 >;
  1952. };
  1954. spi1-rx {
  1955. rockchip,pins = < 0x07 0x0e 0x02 0x77 >;
  1956. phandle = < 0x22 >;
  1957. };
  1959. spi1-tx {
  1960. rockchip,pins = < 0x07 0x0f 0x02 0x77 >;
  1961. phandle = < 0x21 >;
  1962. };
  1963. };
  1965. spi2 {
  1967. spi2-cs1 {
  1968. rockchip,pins = < 0x08 0x03 0x01 0x77 >;
  1969. };
  1971. spi2-clk {
  1972. rockchip,pins = < 0x08 0x06 0x01 0x77 >;
  1973. phandle = < 0x24 >;
  1974. };
  1976. spi2-cs0 {
  1977. rockchip,pins = < 0x08 0x07 0x01 0x77 >;
  1978. phandle = < 0x27 >;
  1979. };
  1981. spi2-rx {
  1982. rockchip,pins = < 0x08 0x08 0x01 0x77 >;
  1983. phandle = < 0x26 >;
  1984. };
  1986. spi2-tx {
  1987. rockchip,pins = < 0x08 0x09 0x01 0x77 >;
  1988. phandle = < 0x25 >;
  1989. };
  1990. };
  1992. uart0 {
  1994. uart0-xfer {
  1995. rockchip,pins = < 0x04 0x10 0x01 0x77 0x04 0x11 0x01 0x76 >;
  1996. phandle = < 0x2c >;
  1997. };
  1999. uart0-cts {
  2000. rockchip,pins = < 0x04 0x12 0x01 0x77 >;
  2001. phandle = < 0x2d >;
  2002. };
  2004. uart0-rts {
  2005. rockchip,pins = < 0x04 0x13 0x01 0x76 >;
  2006. phandle = < 0x7c >;
  2007. };
  2008. };
  2010. uart1 {
  2012. uart1-xfer {
  2013. rockchip,pins = < 0x05 0x08 0x01 0x77 0x05 0x09 0x01 0x76 >;
  2014. phandle = < 0x2e >;
  2015. };
  2017. uart1-cts {
  2018. rockchip,pins = < 0x05 0x0a 0x01 0x77 >;
  2019. };
  2021. uart1-rts {
  2022. rockchip,pins = < 0x05 0x0b 0x01 0x76 >;
  2023. };
  2024. };
  2026. uart2 {
  2028. uart2-xfer {
  2029. rockchip,pins = < 0x07 0x16 0x01 0x77 0x07 0x17 0x01 0x76 >;
  2030. phandle = < 0x2f >;
  2031. };
  2032. };
  2034. uart3 {
  2036. uart3-xfer {
  2037. rockchip,pins = < 0x07 0x07 0x01 0x77 0x07 0x08 0x01 0x76 >;
  2038. phandle = < 0x30 >;
  2039. };
  2041. uart3-cts {
  2042. rockchip,pins = < 0x07 0x09 0x01 0x77 >;
  2043. };
  2045. uart3-rts {
  2046. rockchip,pins = < 0x07 0x0a 0x01 0x76 >;
  2047. };
  2048. };
  2050. uart4 {
  2052. uart4-xfer {
  2053. rockchip,pins = < 0x05 0x0c 0x03 0x77 0x05 0x0d 0x03 0x76 >;
  2054. phandle = < 0x31 >;
  2055. };
  2057. uart4-cts {
  2058. rockchip,pins = < 0x05 0x0e 0x03 0x77 >;
  2059. };
  2061. uart4-rts {
  2062. rockchip,pins = < 0x05 0x0f 0x03 0x76 >;
  2063. };
  2064. };
  2066. tsadc {
  2068. otp-gpio {
  2069. rockchip,pins = < 0x00 0x0a 0x00 0x76 >;
  2070. phandle = < 0x36 >;
  2071. };
  2073. otp-out {
  2074. rockchip,pins = < 0x00 0x0a 0x01 0x76 >;
  2075. phandle = < 0x37 >;
  2076. };
  2077. };
  2079. pwm0 {
  2081. pwm0-pin {
  2082. rockchip,pins = < 0x07 0x00 0x01 0x76 >;
  2083. phandle = < 0x49 >;
  2084. };
  2085. };
  2087. pwm1 {
  2089. pwm1-pin {
  2090. rockchip,pins = < 0x07 0x01 0x01 0x76 >;
  2091. phandle = < 0x4a >;
  2092. };
  2093. };
  2095. pwm2 {
  2097. pwm2-pin {
  2098. rockchip,pins = < 0x07 0x16 0x03 0x76 >;
  2099. phandle = < 0x4b >;
  2100. };
  2101. };
  2103. pwm3 {
  2105. pwm3-pin {
  2106. rockchip,pins = < 0x07 0x17 0x03 0x76 >;
  2107. phandle = < 0x4c >;
  2108. };
  2109. };
  2111. gmac {
  2113. rgmii-pins {
  2114. rockchip,pins = < 0x03 0x1e 0x03 0x76 0x03 0x1f 0x03 0x76 0x03 0x1a 0x03 0x76 0x03 0x1b 0x03 0x76 0x03 0x1c 0x03 0x7b 0x03 0x1d 0x03 0x7b 0x03 0x18 0x03 0x7b 0x03 0x19 0x03 0x7b 0x04 0x00 0x03 0x76 0x04 0x05 0x03 0x76 0x04 0x06 0x03 0x76 0x04 0x09 0x03 0x7b 0x04 0x04 0x03 0x7b 0x04 0x01 0x03 0x76 0x04 0x03 0x03 0x76 >;
  2115. phandle = < 0x3b >;
  2116. };
  2118. rmii-pins {
  2119. rockchip,pins = < 0x03 0x1e 0x03 0x76 0x03 0x1f 0x03 0x76 0x03 0x1c 0x03 0x76 0x03 0x1d 0x03 0x76 0x04 0x00 0x03 0x76 0x04 0x05 0x03 0x76 0x04 0x04 0x03 0x76 0x04 0x01 0x03 0x76 0x04 0x02 0x03 0x76 0x04 0x03 0x03 0x76 >;
  2120. };
  2121. };
  2123. spdif {
  2125. spdif-tx {
  2126. rockchip,pins = < 0x06 0x0b 0x01 0x76 >;
  2127. phandle = < 0x5c >;
  2128. };
  2129. };
  2131. pcfg-pull-none-drv-8ma {
  2132. drive-strength = < 0x08 >;
  2133. phandle = < 0x79 >;
  2134. };
  2136. pcfg-pull-up-drv-8ma {
  2137. bias-pull-up;
  2138. drive-strength = < 0x08 >;
  2139. phandle = < 0x7a >;
  2140. };
  2142. backlight {
  2144. bl-en {
  2145. rockchip,pins = < 0x07 0x02 0x00 0x76 >;
  2146. };
  2147. };
  2149. buttons {
  2151. pwrbtn {
  2152. rockchip,pins = < 0x00 0x05 0x00 0x77 >;
  2153. phandle = < 0x83 >;
  2154. };
  2155. };
  2157. eth_phy {
  2159. eth-phy-pwr {
  2160. rockchip,pins = < 0x00 0x06 0x00 0x76 >;
  2161. };
  2162. };
  2164. pmic {
  2166. pmic-int {
  2167. rockchip,pins = < 0x00 0x04 0x00 0x77 >;
  2168. phandle = < 0x42 >;
  2169. };
  2171. dvs-1 {
  2172. rockchip,pins = < 0x00 0x0b 0x00 0x78 >;
  2173. phandle = < 0x44 >;
  2174. };
  2176. dvs-2 {
  2177. rockchip,pins = < 0x00 0x0c 0x00 0x78 >;
  2178. phandle = < 0x45 >;
  2179. };
  2180. };
  2182. sdio-pwrseq {
  2184. wifi-enable-h {
  2185. rockchip,pins = < 0x04 0x1c 0x00 0x76 >;
  2186. phandle = < 0x82 >;
  2187. };
  2189. chip-enable-h {
  2190. rockchip,pins = < 0x04 0x1b 0x00 0x76 >;
  2191. phandle = < 0x81 >;
  2192. };
  2193. };
  2195. usb {
  2197. host-vbus-drv {
  2198. rockchip,pins = < 0x00 0x0e 0x00 0x76 >;
  2199. };
  2201. pwr-3g {
  2202. rockchip,pins = < 0x07 0x08 0x00 0x76 >;
  2203. };
  2204. };
  2206. wireless-bluetooth {
  2208. uart0-gpios {
  2209. rockchip,pins = < 0x04 0x13 0x00 0x76 >;
  2210. phandle = < 0x7d >;
  2211. };
  2212. };
  2213. };
  2215. memory {
  2216. reg = < 0x00 0x00 0x00 0x80000000 >;
  2217. device_type = "memory";
  2218. };
  2220. wireless-bluetooth {
  2221. compatible = "bluetooth-platdata";
  2222. uart_rts_gpios = < 0x3c 0x13 0x01 >;
  2223. pinctrl-names = "default\0rts_gpio";
  2224. pinctrl-0 = < 0x7c >;
  2225. pinctrl-1 = < 0x7d >;
  2226. BT,reset_gpio = < 0x3c 0x1d 0x00 >;
  2227. BT,wake_gpio = < 0x3c 0x1a 0x00 >;
  2228. BT,wake_host_irq = < 0x3c 0x1f 0x00 >;
  2229. status = "okay";
  2230. };
  2232. wireless-wlan {
  2233. compatible = "wlan-platdata";
  2234. rockchip,grf = < 0x38 >;
  2235. wifi_chip_type = "ap6212";
  2236. sdio_vref = < 0x708 >;
  2237. WIFI,host_wake_irq = < 0x3c 0x1e 0x00 >;
  2238. status = "okay";
  2239. };
  2241. external-gmac-clock {
  2242. compatible = "fixed-clock";
  2243. #clock-cells = < 0x00 >;
  2244. clock-frequency = < 0x7735940 >;
  2245. clock-output-names = "ext_gmac";
  2246. phandle = < 0x39 >;
  2247. };
  2249. io-domains {
  2250. compatible = "rockchip,rk3288-io-voltage-domain";
  2251. rockchip,grf = < 0x38 >;
  2252. flash0-supply = < 0x7e >;
  2253. gpio30-supply = < 0x47 >;
  2254. wifi-supply = < 0x7f >;
  2255. sdcard-supply = < 0x11 >;
  2256. };
  2258. sdio-pwrseq {
  2259. compatible = "mmc-pwrseq-simple";
  2260. clocks = < 0x80 0x01 >;
  2261. clock-names = "ext_clock";
  2262. pinctrl-names = "default";
  2263. pinctrl-0 = < 0x81 0x82 >;
  2264. reset-gpios = < 0x3c 0x1c 0x01 0x3c 0x1b 0x01 >;
  2265. phandle = < 0x12 >;
  2266. };
  2268. gpio-keys {
  2269. compatible = "gpio-keys";
  2270. #address-cells = < 0x01 >;
  2271. #size-cells = < 0x00 >;
  2272. autorepeat;
  2273. pinctrl-names = "default";
  2274. pinctrl-0 = < 0x83 >;
  2276. button@0 {
  2277. gpios = < 0x41 0x05 0x01 >;
  2278. linux,code = < 0x74 >;
  2279. label = "GPIO Key Power";
  2280. linux,input-type = < 0x01 >;
  2281. wakeup-source;
  2282. debounce-interval = < 0x64 >;
  2283. };
  2284. };
  2286. gpio-leds {
  2287. compatible = "gpio-leds";
  2289. act-led {
  2290. gpios = < 0x84 0x18 0x00 >;
  2291. linux,default-trigger = "mmc0";
  2292. };
  2294. heartbeat-led {
  2295. gpios = < 0x84 0x19 0x00 >;
  2296. linux,default-trigger = "heartbeat";
  2297. };
  2299. pwr-led {
  2300. gpios = < 0x41 0x03 0x00 >;
  2301. linux,default-trigger = "default-on";
  2302. };
  2303. };
  2305. sound {
  2306. compatible = "simple-audio-card";
  2307. simple-audio-card,format = "i2s";
  2308. simple-audio-card,name = "rockchip,tinker-codec";
  2309. simple-audio-card,mclk-fs = < 0x200 >;
  2311. simple-audio-card,codec {
  2312. sound-dai = < 0x85 >;
  2313. };
  2315. simple-audio-card,cpu {
  2316. sound-dai = < 0x86 >;
  2317. };
  2318. };
  2320. vsys-regulator {
  2321. compatible = "regulator-fixed";
  2322. regulator-name = "vcc_sys";
  2323. regulator-min-microvolt = < 0x4c4b40 >;
  2324. regulator-max-microvolt = < 0x4c4b40 >;
  2325. regulator-always-on;
  2326. regulator-boot-on;
  2327. phandle = < 0x46 >;
  2328. };
  2330. sdmmc-regulator {
  2331. compatible = "regulator-fixed";
  2332. gpio = < 0x87 0x0b 0x01 >;
  2333. pinctrl-names = "default";
  2334. pinctrl-0 = < 0x88 >;
  2335. regulator-name = "vcc_sd";
  2336. regulator-min-microvolt = < 0x325aa0 >;
  2337. regulator-max-microvolt = < 0x325aa0 >;
  2338. startup-delay-us = < 0x186a0 >;
  2339. vin-supply = < 0x47 >;
  2340. };
  2342. flash-regulator {
  2343. compatible = "regulator-fixed";
  2344. regulator-name = "vcc_flash";
  2345. regulator-min-microvolt = < 0x1b7740 >;
  2346. regulator-max-microvolt = < 0x1b7740 >;
  2347. vin-supply = < 0x47 >;
  2348. phandle = < 0x7e >;
  2349. };
  2350. };
  2351.  
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