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  2. --- drivers/hwmon/k10temp.c 2017-09-14 13:25:55.605917971 +0200
  3. +++ drivers/hwmon/k10temp.c 2017-09-14 13:25:55.605917971 +0200
  4. @@ -36,6 +36,10 @@
  5. /* Provide lock for writing to NB_SMU_IND_ADDR */
  6. static DEFINE_MUTEX(nb_smu_ind_mutex);
  8. +#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
  9. +#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
  10. +#endif
  11. +
  12. /* CPUID function 0x80000001, ebx */
  13. #define CPUID_PKGTYPE_MASK 0xf0000000
  14. #define CPUID_PKGTYPE_F 0x00000000
  15. @@ -61,31 +65,72 @@
  16. */
  17. #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
  19. -static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
  20. - int offset, u32 *val)
  21. +/* F17h M01h Access througn SMN */
  22. +#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
  23. +
  24. +struct k10temp_data {
  25. + struct pci_dev *pdev;
  26. + void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
  27. + int temp_offset;
  28. +};
  29. +
  30. +struct tctl_offset {
  31. + u8 model;
  32. + char const *id;
  33. + int offset;
  34. +};
  35. +
  36. +static const struct tctl_offset tctl_offset_table[] = {
  37. + { 0x17, "AMD Ryzen 7 1600X", 20000 },
  38. + { 0x17, "AMD Ryzen 7 1700X", 20000 },
  39. + { 0x17, "AMD Ryzen 7 1800X", 20000 },
  40. + { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
  41. + { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
  42. + { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
  43. + { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
  44. + { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
  45. +};
  46. +
  47. +static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
  48. +{
  49. + pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
  50. +}
  51. +
  52. +static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
  53. + unsigned int base, int offset, u32 *val)
  54. {
  55. mutex_lock(&nb_smu_ind_mutex);
  56. pci_bus_write_config_dword(pdev->bus, devfn,
  57. - 0xb8, offset);
  58. + base, offset);
  59. pci_bus_read_config_dword(pdev->bus, devfn,
  60. - 0xbc, val);
  61. + base + 4, val);
  62. mutex_unlock(&nb_smu_ind_mutex);
  63. }
  65. +static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
  66. +{
  67. + amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
  68. + F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
  69. +}
  70. +
  71. +static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
  72. +{
  73. + amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
  74. + F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
  75. +}
  76. +
  77. static ssize_t temp1_input_show(struct device *dev,
  78. struct device_attribute *attr, char *buf)
  79. {
  80. + struct k10temp_data *data = dev_get_drvdata(dev);
  81. u32 regval;
  82. - struct pci_dev *pdev = dev_get_drvdata(dev);
  83. + int temp;
  85. - if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
  86. - amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
  87. - F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
  88. - &regval);
  89. - } else {
  90. - pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval);
  91. - }
  92. - return sprintf(buf, "%u\n", (regval >> 21) * 125);
  93. + data->read_tempreg(data->pdev, &regval);
  94. + temp = (regval >> 21) * 125;
  95. + temp -= data->temp_offset;
  96. +
  97. + return sprintf(buf, "%u\n", temp);
  98. }
  100. static ssize_t temp1_max_show(struct device *dev,
  101. @@ -98,11 +143,12 @@
  102. struct device_attribute *devattr, char *buf)
  103. {
  104. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  105. + struct k10temp_data *data = dev_get_drvdata(dev);
  106. int show_hyst = attr->index;
  107. u32 regval;
  108. int value;
  110. - pci_read_config_dword(dev_get_drvdata(dev),
  111. + pci_read_config_dword(data->pdev,
  112. REG_HARDWARE_THERMAL_CONTROL, &regval);
  113. value = ((regval >> 16) & 0x7f) * 500 + 52000;
  114. if (show_hyst)
  115. @@ -119,7 +165,8 @@
  116. struct attribute *attr, int index)
  117. {
  118. struct device *dev = container_of(kobj, struct device, kobj);
  119. - struct pci_dev *pdev = dev_get_drvdata(dev);
  120. + struct k10temp_data *data = dev_get_drvdata(dev);
  121. + struct pci_dev *pdev = data->pdev;
  123. if (index >= 2) {
  124. u32 reg_caps, reg_htc;
  125. @@ -187,7 +234,9 @@
  126. {
  127. int unreliable = has_erratum_319(pdev);
  128. struct device *dev = &pdev->dev;
  129. + struct k10temp_data *data;
  130. struct device *hwmon_dev;
  131. + int i;
  133. if (unreliable) {
  134. if (!force) {
  135. @@ -199,7 +248,31 @@
  136. "unreliable CPU thermal sensor; check erratum 319\n");
  137. }
  139. - hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", pdev,
  140. + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  141. + if (!data)
  142. + return -ENOMEM;
  143. +
  144. + data->pdev = pdev;
  145. +
  146. + if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
  147. + boot_cpu_data.x86_model == 0x70))
  148. + data->read_tempreg = read_tempreg_nb_f15;
  149. + else if (boot_cpu_data.x86 == 0x17)
  150. + data->read_tempreg = read_tempreg_nb_f17;
  151. + else
  152. + data->read_tempreg = read_tempreg_pci;
  153. +
  154. + for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
  155. + const struct tctl_offset *entry = &tctl_offset_table[i];
  156. +
  157. + if (boot_cpu_data.x86 == entry->model &&
  158. + strstr(boot_cpu_data.x86_model_id, entry->id)) {
  159. + data->temp_offset = entry->offset;
  160. + break;
  161. + }
  162. + }
  163. +
  164. + hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
  165. k10temp_groups);
  166. return PTR_ERR_OR_ZERO(hwmon_dev);
  167. }
  168. @@ -214,6 +287,7 @@
  169. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
  170. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
  171. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
  172. + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
  173. {}
  174. };
  175. MODULE_DEVICE_TABLE(pci, k10temp_id_table);
  176.  
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